1. Field of the Invention
The present invention relates to dual port memories, and particularly to special purpose dual port static random access memories (SRAMs) used as color lookup tables in display systems. More particularly, the invention relates to a high speed CMOS dual port SRAM having a read/write port and a very fast read-only port.
2. Description of the Background
It is often desirable to optimize the design of a memory cell to meet the needs of a particular application. For instance, static random access memories (SRAMs) have been implemented for a variety of applications. One particular application which has unique requirements is that of the color lookup table in display systems. Prior art integrated circuits which provide this function include the BT458, and similar parts manufactured by Brooktree Corporation, and the Am81C458 manufactured by Advanced Micro Devices, Inc. In these integrated circuits, a color lookup table is provided which stores codes that identify specific colors to be displayed on a video display screen.
For each picture element, or pixel, in the screen, the color lookup table is accessed with an address, and the code stored in the table at that address identifies the color of the pixel. This addressing occurs at a very high rate of speed which is determined by the frequency at which pixels must be refreshed in the display system. Also, when the selections of colors available in the color lookup table must be changed, updated, or monitored, a central processing unit in the display system must have access to the entries in the table. For this purpose, a second, slower port, which allows reading and writing to memory elements in the table, is provided for CPU access.
Because the CPU clock is unrelated to the speed at which the color information must be accessed for the display path, the display path and CPU path must operate independently and asynchronously of one another. The asynchronous and independent nature of the ports, together with the very high speed at which the display port must perform, create unique design criteria for an SRAM in this application.
The prior art devices referred to above each use a ten transistor SRAM cell with a differential sense amplifier, such as described in U.S. Pat. No. 4,905,189. This SRAM cell is relatively large and requires complex differential sensing schemes in order to achieve the necessary speed of operation for the video display port. The size and complexity of this prior art memory cell limited the speed at which it could operate. In addition, the size of the cell translated into a very large SRAM area on the integrated circuit. Large area increases the cost of manufacturing the chip for a variety of reasons well known in the art. U.S. Pat. No. 4,768,172 to Sasaki teaches an SRAM cell having a read-write port and a read-only port, in which the read-only port is isolated from the memory cell such that reading from the read-only port does not affect current flow within the memory cell. This isolation enhances the ability to simultaneously and asynchronously operate both ports. The patent does not, however, provide any specific adaptations of the memory cell for use in a color lookup table, or any other such application requiring very high-speed read access. Furthermore, the patent does not teach how to optimally utilize the available read-only bandwidth. Finally, the patent does not teach a way of optimally fitting a given size array of the memory cells within a given chip area.
Accordingly, it is desirable to provide a memory cell and an overall memory architecture which optimizes the requirements for independent and asynchronous ports, and very high-speed display access paths, while minimizing the size and complexity of the memory cell. The memory architecture should have an optimally reduced footprint, and should be provided with means for optimally utilizing the available speed of the read-only port, for very high-speed operations such as color lookup table reading in a color video display system.